Japanese Patent Application No. 2001-327239 filed on Oct. 25, 2001 and Japanese Patent Application No. 2002-238017 filed on Aug. 19, 2002, are hereby incorporated by reference in their entirety.
The present invention relates to a semiconductor wafer, a method of manufacturing a semiconductor wafer having bumps, a semiconductor chip having bumps and a method of manufacturing the same, a semiconductor device, a circuit board, and electronic equipment.
As the degree of integration of a semiconductor integrated circuit is increased and the size of a semiconductor chip is decreased, mounting technology capable of connecting terminals at a minute pitch has been demanded. As examples of mounting technology capable of easily dealing with such a demand, TAB (Tape Automated Bonding) mounting used for a TCP (Tape Carrier Package) and flip-chip mounting used for a CSP (Chip Size Package) can be given.
In the above mounting technology, bumps are generally formed on pads of the semiconductor chip. Au bumps are typically used as the bumps and generally formed by electroplating. A method of forming Au bump electrodes by electroplating is described below.
FIG. 16 is a cross-sectional view showing an Au bump in a conventional semiconductor chip. A pad 502, which is part of an interconnect linked with an inner integrated circuit, is covered with a passivation film 504 excluding the surface of an electrical connection region.
An under-bump metal layer (laminate of a barrier metal layer and an adhesive metal layer) 506 is formed by using a sputtering method. A resist layer 508 for forming bumps which exposes the electrical connection region of the pad 502 and its peripheral region is formed by using photolithographic technology. Au is grown by electroplating corresponding to the pattern of the resist layer 508. After removing the resist layer 508, the under-bump metal layer 506 is wet-etched corresponding to the type of the under-bump metal layer 506 using the grown Au as a mask. A bump 510 is formed by subsequent annealing and the like. A cleaning step is appropriately performed during the process. Since bump formation by electroplating is a long process, further reduction and rationalization of the process are demanded.
To deal with this demand, formation of bumps by electroless plating has been proposed. If the bumps are formed by electroless plating, it is unnecessary to perform at least the step of forming the under-bump metal layer by sputtering and the step of etching the under-bump metal layer. Moreover, it is expected that formation of a resist for growth of plating can be omitted. This enables the process to be significantly reduced, whereby the bumps are formed at low cost.
Conventionally, aluminum pads are subjected to a zincate treatment as a pretreatment for plating when forming the bumps by electroless plating. Specifically, a semiconductor wafer is immersed in a treatment solution including Zn ions, whereby the surface of the pads is replaced by Zn according to the reaction shown by 2Al+3Zn2+xe2x86x922Al3++3Zn. The entire semiconductor wafer is then immersed in a plating solution (treatment solution for plating), thereby causing a plating metal to be deposited. The process maybe rationalized by batch processing in which a plurality of semiconductor wafers is immersed in the plating solution.
The aluminum pads which become GND electrodes are electrically connected with an Si substrate of the semiconductor wafer. The Si substrate is electrically connected with the treatment solution. When electrons in the Si substrate are released into the treatment solution, the potential of the aluminum pads is changed. Since the amount of electrons used for a chemical reaction is decreased by such a grounding effect, ionic bonding rarely occurs, whereby replacement of the surface of the aluminum pads by Zn is insufficient in the zincate treatment. Moreover, the plating rate is changed by the grounding effect, whereby deposition of the plating metal is affected.
There is a case where a considerable amount of resist is thickly applied to the back side and a region near the periphery (from the periphery of the surface to the side) of the semiconductor wafer in order to prevent influence of the grounding effect. The zincate treatment and the plating treatment are performed while preventing the plating solution from coming in contact with a region near the periphery and the back side of the semiconductor wafer in this manner.
A resist is applied to the back side of the semiconductor wafer while chucking (absorbing under vacuum) the side on which the bumps are formed (main surface of the semiconductor wafer) on a rotating table of a spin coater. In this case, the bump formation side must be prevented from being damaged so that the subsequent growth of plating is not affected. Since the deposition and growth of the plating metal is determined corresponding to the potential of a region with which the pads are electrically connected, even if the resist is applied to the back side of the semiconductor wafer, it is difficult to form bumps having a uniform height by high-quality electroless plating.
A semiconductor wafer according to a first aspect of the present invention comprises:
a plurality of monolithic integrated circuits formed in a semiconductor crystal for realizing a function of a plurality of semiconductor chips;
a plurality of pads formed in a plurality of first regions to be the plurality of semiconductor chips; and
a conductor formed in a layer lower than the pads through a second region, which is located between two of the first regions, and electrically connecting at least two of the pads.
A semiconductor wafer according to a second aspect of the present invention comprises:
a plurality of monolithic integrated circuits formed in a semiconductor crystal for realizing a function of a plurality of semiconductor chips;
a plurality of pads formed in a plurality of first regions to be the plurality of semiconductor chips; and
a conductive film formed on the pads through a second region, which is located between two of the first regions, and electrically connecting at least two of the pads,
wherein the conductive film is formed so that the at least two of the pads are electrically isolated when a portion of the conductive film in the second region is removed.
A method of manufacturing a semiconductor wafer having bumps according to a third aspect of the present invention comprises:
forming the bumps by electroless plating on respective pads of a semiconductor wafer having a plurality of monolithic integrated circuits formed in a semiconductor crystal for realizing a function of a plurality of semiconductor chips,
wherein the plurality of pads is formed in a plurality of first regions to be the plurality of semiconductor chips, and
wherein the electroless plating is performed in a state in which at least two of the pads are electrically connected by a conductor formed in a layer lower than the pads through a second region, which is located between two of the first regions.
A method of manufacturing a semiconductor wafer having bumps according to a fourth aspect of the present invention comprises:
forming a conductive film on a plurality of pads of a semiconductor wafer having a plurality of monolithic integrated circuits formed in a semiconductor crystal for realizing a function of a plurality of semiconductor chips so as to electrically connect at least two of the pads; and
forming bumps on the conductive film in a region over each of the pads by electroless plating.
A method of manufacturing a semiconductor chip having bumps according to a fifth aspect of the present invention comprises cutting a semiconductor wafer,
wherein the semiconductor wafer includes:
a plurality of monolithic integrated circuits formed in a semiconductor crystal for realizing a function of a plurality of semiconductor chips;
a plurality of pads formed in a plurality of first regions to be the plurality of semiconductor chips;
a conductor formed in a layer lower than the pads through a second region, which is located between two of the first regions, and electrically connecting at least two of the pads; and
bumps formed on at least two of the electrically connected pads, respectively, and
wherein the semiconductor wafer is cut along the second region.
A method of manufacturing a semiconductor chip having bumps according to a sixth aspect of the present invention comprises cutting a semiconductor wafer,
wherein the semiconductor wafer includes:
a plurality of monolithic integrated circuits formed in a semiconductor crystal for realizing a function of a plurality of semiconductor chips;
a plurality of pads formed in a plurality of first regions to be the plurality of semiconductor chips;
a conductive film formed on the pads through a second region, which is located between two of the first regions, and electrically connecting at least two of the pads; and
bumps formed on the conductive film in a region over the respective pads, and
wherein the semiconductor wafer is cut along the second region.
A semiconductor chip having bumps according to a seventh aspect of the present invention is manufactured by using the above method.
A semiconductor device according to an eight aspect of the present invention comprises:
the above semiconductor chip having bumps;
a substrate on which the semiconductor chip having the bumps is mounted; and
external terminals.
A circuit board according to a ninth aspect of the present invention includes the above semiconductor chip having bumps mounted on the circuit board.
A circuit board according to a tenth aspect of the present invention includes the above semiconductor device mounted on the circuit board.
Electronic equipment according to an eleventh aspect of the present invention comprises the above semiconductor device.